Dissecting the Blackrock Neurotech Utah Array

Despite not having a public profile like Neuralink, Blackrock Neurotech's is arguably the most well-known BCI company in the neuroscience community, having collected over 2 decades of research in humans. The Utah Electrode Array comprises 96-100 penetrating silicon shanks arranged in a 10×10 grid, each shank measuring 1.5 mm in length with 400 μm center-to-center spacing (Campbell et al., 1991). This architecture has remained consistent since its development at the University of Utah in the 1990s, though manufacturing processes have undergone significant evolution, particularly the transition to wafer-scale production post-2009 and the breakthrough bilayer insulation that extended functional lifetimes tenfold.

In this post, I review Blackrock Neurotech's manufacturing process from publicly available information.

Early Manufacturing Approach (Pre-2009)

Silicon Wafer Preparation and Aluminum Doping

The original Utah Array manufacturing process begins with n-type monocrystalline silicon wafers - semiconductor-grade silicon with carefully controlled crystal orientation, typically (100) or (111) planes (Campbell et al., 1991). The choice of monocrystalline silicon over polycrystalline variants is critical because the subsequent anisotropic etching process relies on the crystallographic planes to form precise pyramidal structures.

Aluminum is deposited on one face of the silicon wafer, creating a thin uniform layer typically 500-1000 nm thick. The wafer then undergoes high-temperature processing at 1150°C in an inert atmosphere for several hours (Campbell et al., 1991). During this thermal treatment, aluminum atoms diffuse into the silicon crystal lattice through solid-state diffusion, a process called thermomigration. The aluminum creates heavily doped P+ conductive pathways that penetrate vertically through the wafer thickness, forming what will become the conductive cores of the electrode shanks. This eliminates the need for separate metal traces inside each silicon needle.

The depth and profile of aluminum diffusion are controlled by time and temperature - longer processing times and higher temperatures drive deeper penetration. The process requires careful control to avoid excessive diffusion that would create shanks with poor electrical conductivity or compromised mechanical properties.

Wafer Dicing and Array Isolation

After aluminum thermomigration, the silicon wafers are diced into individual array footprints using precision diamond saws or laser cutting. Each piece represents one future 10×10 electrode array, typically measuring 4×4 mm in base dimensions (Campbell et al., 1991). This dicing step in the early process meant each array would be processed individually through subsequent steps - a limitation that reduced manufacturing efficiency and consistency compared to the later wafer-scale approach.

Anisotropic Wet Etching Creates Pyramidal Shanks

The diced silicon pieces are immersed in hot potassium hydroxide (KOH) solution, typically at concentrations of 20-40% KOH in water at temperatures of 60-80°C (Campbell et al., 1991). KOH is a powerful anisotropic etchant that dissolves silicon at dramatically different rates depending on the crystallographic plane orientation. For silicon wafers oriented along the (100) plane, KOH etches the (100) planes approximately 100-400 times faster than the (111) planes. This differential etching naturally forms pyramidal structures with sidewalls aligned to the (111) planes, creating needle-like shanks that taper to sharp tips.

The angle of the pyramid sides is determined by the crystallographic geometry - for (100) wafers, the (111) sidewalls form 54.74° angles relative to the base. Etch depth is controlled by immersion time, with 1.5 mm tall shanks typically requiring 6-12 hours depending on KOH concentration and temperature. The process achieves remarkable dimensional consistency with less than 3% variation in shank height across the array (Campbell et al., 1991) - a testament to the precision of crystallographic etching versus mechanical machining.

The aluminum-doped regions etch at different rates than undoped silicon, creating preferential etching that helps define individual shanks. After etching completes, the arrays are thoroughly rinsed in deionized water and dried, revealing the characteristic forest of silicon needles.

Platinum Metallization via Magnetron Sputtering

DC magnetron sputtering deposits the platinum recording surfaces onto the silicon shanks. The process occurs in a vacuum chamber where argon ions bombard a platinum target, ejecting platinum atoms that travel through the vacuum and condense on the silicon array surface (Negi et al., 2010). A critical challenge is achieving conformal coating on the three-dimensional pyramidal geometry - simple line-of-sight deposition would coat only the top and sides of the shanks, leaving shadowed regions uncoated. To address this, Blackrock employs substrate rotation and tilting during deposition, ensuring platinum coverage from multiple angles.

The metallization sequence begins with a titanium adhesion layer of 50 nm, sputtered first to promote platinum adhesion to silicon. Titanium forms titanium silicide at the interface, creating a strong chemical bond. Without this layer, platinum would delaminate during subsequent processing or chronic implantation. The platinum recording layer follows at 200 nm thickness, DC sputtered at approximately 90W power in argon plasma (Negi et al., 2010). Film thickness is measured using quartz crystal monitors in the deposition chamber and verified post-deposition using profilometry or cross-sectional SEM. The 200 nm platinum layer must be thick enough to provide low electrical resistance and mechanical durability, but thin enough to avoid excessive stiffness that could cause delamination from the underlying silicon during mechanical stress.

Iridium Oxide Coating for Enhanced Performance

Sputtered iridium oxide films (SIROF) are applied to the electrode tips through reactive magnetron sputtering (Negi et al., 2010). This process differs from the platinum deposition by introducing oxygen gas into the sputtering chamber alongside argon. An iridium target is bombarded with argon ions while oxygen molecules are present in the chamber. The ejected iridium atoms react with oxygen either in the gas phase or on the substrate surface, forming iridium oxide - primarily IrO₂ with some Ir₂O₃ - as the deposited film.

The oxygen partial pressure, RF power, and substrate temperature are carefully controlled to achieve the desired film composition and morphology. Blackrock's optimized SIROF process creates 400-1100 nm thick coatings with a nanoporous surface structure (Negi et al., 2010). This porosity dramatically increases the electrochemically active surface area - the coating acts like a microscopic sponge, providing far more reactive surface than a flat platinum electrode of the same geometric dimensions. The resulting electrodes achieve charge storage capacity of 1.9 mC/cm² versus 0.05-0.15 mC/cm² for bare platinum, and impedances of 20-50 kΩ at 1 kHz versus 500-2000 kΩ for bare platinum of similar size (Negi et al., 2010). This 10-50× improvement in electrochemical performance comes from the reversible Ir(III)/Ir(IV) redox reactions that allow the oxide to store and release charge without causing faradaic reactions that would corrode the electrode or damage tissue.

The Bilayer Insulation Breakthrough

The insulation process underwent a critical evolution that represents Blackrock's most significant manufacturing innovation. The original approach used Parylene-C chemical vapor deposition to create a 3-5 μm conformal coating over the entire array (Rousche et al., 2001). While this provided excellent electrical insulation and biocompatibility, chronic implant studies showed functional lifetimes of only approximately 100 days before significant electrode failures occurred.

In 2013, researchers discovered that adding an ultra-thin aluminum oxide layer beneath the Parylene-C dramatically improved durability (Barrese et al., 2016). The current bilayer process begins with atomic layer deposition (ALD) of 52 nm of aluminum oxide. ALD is a specialized technique that deposits materials one atomic layer at a time through sequential, self-limiting chemical reactions. For aluminum oxide, the array is exposed to trimethylaluminum vapor, which reacts with surface hydroxyl groups, depositing a monolayer of aluminum. Excess precursor is purged from the chamber, then water vapor is introduced, reacting with the aluminum to form aluminum oxide and creating new hydroxyl groups. The cycle repeats hundreds of times to build up the 52 nm film.

ALD's strength is producing pinhole-free, perfectly conformal coatings even on complex 3D geometries like the Utah Array shanks. The atomic-level thickness control ensures uniform insulation regardless of surface topology. Following the aluminum oxide layer, Parylene-C CVD applies the 3-5 μm outer coating via the standard three-stage vapor deposition process - sublimation at 150°C, pyrolysis at 680°C, and polymerization at 15-25°C (Rodger et al., 2008).

This bilayer approach increased functional lifetime from approximately 100 days to over 1,044 days - a tenfold improvement (Barrese et al., 2016). Atomic layer deposited aluminum oxide provides an exceptional moisture barrier with water vapor transmission rates on the order of 10⁻¹⁰ g·mm/m²·day, but dissolves when exposed directly to aqueous environments (Xie et al., 2014). The Parylene-C outer layer serves dual functions - acting as an ion barrier and preventing direct contact between the aluminum oxide and body fluids. This combination overcomes the primary failure mode of Parylene-only encapsulation, where moisture condenses at the interface between the coating and device surface, leading to delamination and electrical shorts

Laser Ablation for Tip Exposure

KrF excimer laser ablation at 248 nm wavelength selectively removes the bilayer insulation from the electrode tips (Barrese et al., 2016). The UV laser energy photochemically decomposes both the Parylene-C and aluminum oxide through direct bond breaking. Approximately 200 laser pulses are applied to each electrode tip, with pulse energy and focus carefully controlled to completely remove insulation down to the underlying iridium oxide while minimizing damage to the recording surface. The laser system employs computer-controlled positioning stages that sequentially target each of the 96-100 electrode tips with submicron accuracy. Post-ablation inspection using optical microscopy or SEM verifies complete insulation removal and absence of debris or cracking around the exposed tips.

Evolution to Wafer-Scale Manufacturing (Post-2009)

Blackrock transitioned from processing individual diced arrays to wafer-scale manufacturing, fundamentally improving production efficiency and consistency. In this approach, entire wafers proceed through all processing steps before final singulation into individual devices.

The modified process flow begins with aluminum thermomigration performed on whole wafers, creating doped regions in an arrayed pattern across the wafer surface. Photolithography and etching then define the boundaries between individual arrays - rather than dicing before KOH etching, photoresist masks pattern the wafer into grid arrays, with etch-resistant coatings protecting regions that should not be etched. KOH anisotropic etching creates the pyramidal shanks across multiple arrays simultaneously, with all arrays on a single wafer experiencing identical etch conditions, improving dimensional uniformity compared to individually processed batches.

Metallization, iridium oxide coating, and bilayer insulation coat the entire wafer of arrays in single process runs, dramatically improving throughput and reducing batch-to-batch variation. Laser ablation deinsulates tips on all arrays while still in wafer form, with automated systems sequentially addressing hundreds or thousands of electrode tips. Only after all microfabrication steps are complete does wafer dicing separate individual arrays.

This wafer-scale approach offers multiple advantages. Throughput increases from individual handling to processing 20-50 arrays per wafer run. Uniformity improves as all devices on a wafer experience identical deposition, etching, and coating conditions. Costs reduce through amortized equipment time and cleanroom overhead across multiple devices. Quality control becomes easier with in-line monitoring and statistical process control across larger batches.

CerePort Integration and System Assembly

Individual Utah Arrays are attached to CerePort titanium pedestals through gold wire bonding (Barrese et al., 2013). The CerePort serves as the percutaneous connector - a titanium pedestal that protrudes through the skull, providing the interface between the implanted array and external electronics. Thermosonic bonding is used, where 25 μm (1 mil) diameter insulated gold wire is fed through a capillary tool, pressed against contact pads on the array base while ultrasonic energy and substrate heat create a metallic bond, routed to corresponding pads on the CerePort, bonded a second time, and cut. Each of the 96-100 electrodes requires an individual wire bond, making this a time-intensive process. The bonds must withstand years of mechanical stress from skull movement and temperature cycling.

The CerePort base is sealed using medical-grade silicone (MED-4211, NuSil Technology), which is applied to the backside of the array and wire bundle to secure bond connections, increase mechanical strength, and protect against handling forces and fluid ingress (Xie et al., 2014). For fully implantable wireless neural interface variants, a two-piece titanium enclosure is hermetically sealed by laser welding to protect all active electronics from the biological environment.

Signal Processing Architecture Evolution

Blackrock has developed several generations of signal acquisition electronics, each representing different manufacturing and integration philosophies. Early systems employed analog unity-gain headstages mounted directly on the CerePort pedestal. These simple buffer amplifiers - essentially voltage followers with very high input impedance exceeding 1 GΩ - prevented signal degradation during transmission through ribbon cables to front-end amplifiers located outside the body (Barrese et al., 2013). Manufacturing these headstages involves standard PCB assembly with surface-mount operational amplifiers, passive components for filtering, connector interfaces, and conformal coating for moisture protection.

Modern systems integrate "Honey Badger" application-specific integrated circuits that perform proximal analog-to-digital conversion in digital CerePlex headstages (Blackrock Neurotech, 2024). These ASICs contain low-noise preamplifiers for each channel, programmable gain stages, 15.5-bit ADCs achieving 0.353 μV resolution, digital multiplexing circuitry, and HDMI connector drivers. Manufacturing involves custom ASIC fabrication through semiconductor foundries, PCB design with high-speed digital traces, precise assembly to maintain signal integrity, and shielding to prevent electromagnetic interference. Converting to digital signals at the headstage dramatically improves noise immunity - digital data transmitted through HDMI cables is far less susceptible to electrical interference than analog signals in ribbon cables.

The external Cerebus Neural Signal Processor samples at 30 kHz with 16-bit resolution and 250 nV least significant bit, applying hardware bandpass filters from 0.3 Hz to 7.5 kHz and threshold-based spike detection (Blackrock Neurotech, 2024). This rack-mounted unit represents sophisticated mixed-signal electronics manufacturing with multi-layer PCBs, high-speed ADCs and digital signal processors, real-time operating system firmware, and data acquisition software interfaces.

Blackrock also manufactures wireless variants using 2.765 MHz inductive coupling to power 200 mAh lithium-ion batteries. The wireless transceivers include RF telemetry chipsets, inductive coil windings for both implanted and external components, battery management circuitry with charging controllers, and hermetic titanium packaging for implanted components. These wireless systems require additional manufacturing complexity including RF antenna tuning, battery assembly and testing, hermetic feedthrough connectors, and leak testing of sealed packages.

References

1. Campbell, P., Jones, K., Huber, R., Horch, K., & Normann, R. (1991). A silicon-based, three-dimensional neural interface: manufacturing processes for an intracortical electrode array. IEEE Transactions on Biomedical Engineering, 38(8), 758-768. doi:10.1109/10.83588
2. Negi, S., Bhandari, R., Rieth, L., & Solzbacher, F. (2010). In vitro comparison of sputtered iridium oxide and platinum-coated neural implantable microelectrode arrays. Biomedical Materials, 5(1), 015007. doi:10.1088/1748-6041/5/1/015007
3. Rousche, P., Pellinen, D., Pivin Jr., D., Williams, J., Vetter, R., & Kipke, D. (2001). Flexible polyimide-based intracortical electrode arrays with bioactive capability. IEEE Transactions on Biomedical Engineering, 48(3), 361-371. doi:10.1109/10.914800
4. Barrese, J., Aceros, J., & Donoghue, J. (2016). Scanning electron microscopy of chronically implanted intracortical microelectrode arrays in non-human primates. Journal of Neural Engineering, 13(2), 026003. doi:10.1088/1741-2560/13/2/026003
5. Rodger, D., et al. (2008). Flexible parylene-based multielectrode array technology for high-density neural stimulation and recording. Sensors and Actuators B: Chemical, 132(2), 449-460. doi:10.1016/j.snb.2007.10.069
6. Xie, X., et al. (2014). Long-term reliability of Al2O3 and Parylene C bilayer encapsulated Utah electrode array based neural interfaces for chronic implantation. Journal of Neural Engineering, 11(2), 026016. doi:10.1088/1741-2560/11/2/026016
7. Barrese, J., Rao, N., Paroo, K., Triebwasser, C., Vargas-Irwin, C., Franquemont, L., & Donoghue, J. (2013). Failure mode analysis of silicon-based intracortical microelectrode arrays in non-human primates. Journal of Neural Engineering, 10(6), 066014. doi:10.1088/1741-2560/10/6/066014
8. Blackrock Neurotech, . (2024). CerePlex Digital Headstage Product Specifications. [Link]
9. Blackrock Neurotech, . (2024). Cerebus Neural Signal Processing System Instructions for Use. [Link]